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integrated silicon solution, inc. 1 preliminary information rev. 00a 01/26/09 is25c16 copyright ? 2008 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this specifcation and its products at any time without notice. issi products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equip - ment, aerospace systems, or for other applications planned to support or sustain life. it is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. issi assumes no liability arising out of the application or use of any information, products or services described herein. customers are advised to obtain the latest version of this device specifcation before relying on any published information and prior placing orders for products. 16k-bit spi serial electrically erasable prom features ? serial peripheral interface (spi) compatible supports spi modes 0 (0,0) and 3 (1,1) ? wide-voltage operation vcc = 1.8v to 5.5v ? low power cmos operating current less than 1 ma (1.8v) standby current less than 1 a (1.8v) ? block write protection protect 1/4, 1/2, or entire array ? 16-byte page write mode partial page writes allowed ? 10 mhz clock rate (5v) ? self timed write cycles (5 ms typical) ? high-reliability endurance: 1 million cycles per byte data retention: 100 years ? industrial and automotive temperature ranges ? packages: soic/sop, tssop, dfn and csp preliminary information february 2009 the is25c16 is a 16kbit (2048 x 8) electrically erasable prom devices that use the serial peripheral interface (spi) for communications. this eeprom operates in a wide voltage range of 1.8v to 5.5v to be compatible with most application voltages. issi designed this device to be a practical, low-power spi eeprom solution. the device is offered in lead-free, rohs, halogen free or green. the available package types are 8-pin soic, tssop, dfn and csp. the functional features of the is25c16 allow them to be among the most advanced serial non-volatile memo - ries available. each device has a chip-select ( cs) pin, and a 3-wire interface of serial data in (si), se - rial data out (so), and serial clock (sck). while the 3-wire interface of the is25c16 provides for high-speed access, a hold pin allows the memories to ignore the interface in a suspended state; later the hold pin re- activates communication without re-initializing the serial sequence. a status register facilitates a fexible write protection mechanism, and a device-ready bit ( rdy). description
2 integrated silicon solution, inc. preliminary information rev. 00a 01/26/09 is25c16 write protect ( wp): the purpose of this input signal is to initiate hardware write protection mode. this mode prevents the block protection bits and the wpen bit in the status register from being altered. to cause hard ware write protection, must be low at the same time wpen is 1. may be hardwired to vcc or gnd. hold (hold): this input sinal is used to suspend the device in the middle of a serial sequence and tem porarily ignore further communication on the bus (si, so, sck). together with chip select, the allows multiple slaves to share the bus. signal transitions must occur only when sck is low, and be held stable during sck transitions. (see figure 8 for hold timing) to disable this feature, may be hardwired to vcc. pin descriptions cs chip select sck serial data clock si serial data input so serial data output gnd ground v c c power write protect suspends serial input pin descriptions serial clock (sck): this tiin sinal proides syn - chronization between the microcontroller and is25c16. op-codes, byte addresses, and data are latched on si with a rising edge of the sck. data on so is refreshed on the falling edge of sck for spi modes (0,0) and (1,1). serial data input (si): this is the input pin for all data that the is25c16 is required to receive. serial data output (so): this is the output pin for all data transmitted from the is25c16. pin configuration 8-pin dip, soic, and tssop chip select (cs): the cs pin actiates the deice upon power-up, should follow vcc. when the de vice is to be enabled for instruction input, the signal re quires a high-to-low transition. while is stable low, the master and slave will communicate via sck, si, and so signals. upon completion of communication, must be driven high. at this moment, the slave device may start its internal write cycle. when device enters a power-saving standby mode, unless an internal write operation is underway. during this mode, the so pin becomes high impedance. 1 2 3 4 8 7 6 5 cs so wp gnd vcc hol d sck si 8-pad dfn 1 2 3 4 8 7 6 5 so gnd vcc sck si (top view)
integrated silicon solution, inc. 3 preliminary information rev. 00a 01/26/09 is25c16 serial interface description master: the deice that proides a clock sinal slave: the is25c16 is a slave because the clock transmitter/receiver: the is25c16 has both data input (si) and data output (so). msb: the most signifcant bit. it is always the frst bit op-code: the frst byte transmitted to the slave fol lowing cs transition to low. if the op-code is a valid member of the is25c16 instruction set (table 3), then it is decoded appropriately. if the op-code is not valid, block dia gram s ta tus register 2048 x 8 memor y arra y hold cs wp clock so output buffer sck si d ata register mode decode logic gnd vcc address decoder
4 integrated silicon solution, inc. preliminary information rev. 00a 01/26/09 is25c16 status re gister table 1. status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit1 bit 0 wpen x x x bp1 bp0 wen rdy the status register contains 8-bits for write protection control and write status. (see table 1). it is the only region of memory other than the main array that is ac - cessible by the user. the status register is read-only if either: a) hardware write protection is enabled or b) wen is set to 0. if neither is true, it can be modifed by a valid instruction. rdy when rdy = 1, it indicates that the device is busy with a write cycle. rdy = 0 indicates that the device is ready for an instruction. if rdy = 1, the only command that will be handled by the device is read status register. dont care, bits - each of these bits can receive ei - ther 0 or 1, but values will not be retained. when these bits are read from the register, they are always 1. this bit can be used in conjunction with wp pin to enable hardware write protection, which causes the status register to be read-only. the memory array is not protected by this mode. hardware write protection requires that wp = 0 and wpen = 1; it is disabled otherwise. note: wpen cannot be changed from 1 to 0 if the wp pin is already set to low. (see table 4 for data protection relation - ship) 1. x = don't care bit. 2. during internal write cycles, bits 0 to 7 are temporarily 1's. together, these bits represent one of four block protection confgura - tions implemented for the memory array. (see table 2 for details.) bp0 and bp1 are non-volatile cells similar to regular array cells, and factory programmed to 0. the block of memory defned by these bits is always protected, regardless of the setting of wpen, wp , or wen. table 2. block protection status register bits array addresses protected level bp1 bp0 is25c16 0 0 0 none 1(1/4) 0 1 0600h -07ffh 2(1/2) 1 0 0400h -07ffh 3(all) 1 1 0000h -07ffh this bit represents the status of device write protection. if wen = 0, the status register and the entire array is protected from modif - cation, regardless of the setting of wpen, wp pin, or block protection. the only way to set wen to 1 is via the write enable command (wren). wen is reset to 0 upon power-up.
integrated silicon solution, inc. 5 preliminary information rev. 00a 01/26/09 is25c16 write enable (wren) when vcc is initially applied, the device powers up with both status register and entire array in a write-disabled state. upon completion of write disable (wrdi), write status register (wrsr), or write data to array (write), the device resets the wen bit in the status register to 0. prior to any data modifcation, a wren instruction is necessary to set wen to 1. (see figure 2 for timing). write disable (wrdi) the device can be completely protected from modifca tion by resetting wen to 0 through the wrdi instruc tion. (see figure 3 for timing). read status register (rdsr) the read status instruction tells the user the status of write protect enable, the block protection setting (see table 2), the write enable state, and the rdy rdsr is the only instruction accepted when a write cycle is underway. it is recommended that the status of write enable and rdy be checked, especially prior to an attempted modifcation of data. the 8 bits of the status register can be repeatedly output on so after the initial op-code. (see figure 4 for timing). table 3. instruction set name op-code operation address data(si) data (so) wren 0000 x110 set write enable latch - - - wrdi 0000 x100 reset write enable latch - - - rdsr 0000 x101 read status register - - d7-d0,... wrsr 0000 x001 write status register - d7-d0 - read 0000 x011 read data from array a15-a0 - d7-d0,... write 0000 x010 write data to array a15-a0 d7-d0,... - device operation t he operations of the is25c16 are controlled by a set of instructions that are clocked-in serially si pin. (see table 3). to begin an instruction, the chip select ( cs) should be dropped low. subsequently, each low-to-high transition of the clock (sk) will latch a stable value on the si pin. after the 8-bit op-code, it may be appropriate to continue to input an address or data to si, or to output data from so. during data output, values appear on the falling edge of sk. all bits are transferred with msb frst. upon the last bit of communication, but prior to any following low-to-high transi tion of sk, cs should be raised high to end the transaction. the device then would enter standby mode if no internal programming were underway. 1. x = dont care bit. for consistency, it is best to use 0. 2. some address bits are dont care. see table 5. 3. if the bits clocked-in for an op-code are invalid, so remains high impedance, and upon cs going high there is no affect. a valid op-code with an invalid number of bits clocked-in for address or data will cause an attempt to modify the array or status register to be ignored.
6 integrated silicon solution, inc. preliminary information rev. 00a 01/26/09 is25c16 table 5. address key name is25c16 a n a 10- a 0 don't a 15- a 11 care bits write status register (wrsr) this instruction lets the user choose a block protection setting, and set or reset the wpen bit. the values of the other data bits incorporated into wrsr can be 0 or 1, and are not stored in the status register. wrsr will be ignored unless both the following are true: a) wen = 1, due to a prior wren instruction; and b) hardware write protection is not enabled. (see table 4 for de tails). except for the rdy l s tus register remain unchanged until the moment when the write cycle is complete and the register is updated. note: wpen can be changed from 1 to 0 only if wp is already set high. once completed, wen is reset for complete chip write protection. (see figure 5 for timing). read data (read) this instruction begins with the op-code and the 16- bit address, and causes the selected data byte to be shifted out on so. following this frst data byte, addi tional sequential bytes are output. if the data byte in the lowest address in the array, and the output could loop indefnitely. at any time, a rising cs l ol the operation. (see figure 6 for timing). write data (write) the write instruction begins with the op-code, the 16-bit address of the frst byte to be modifed, and the frst data byte. additional data bytes may be written se quentially to the array after the frst byte. each write instruction can affect the contents of a 16 byte page, but no more. the page begins at address xxxxxxxx xxxx0000, and ends with xxxxxxxx xxxx1111. if the last byte of the page is input, the address rolls over to the beginning of the same page. more than 16 data bytes can be input during the same instruction, but upon a completed write cycle, a page would only contain the last 16 bytes. the region of the array defned within block protection cannot be modifed as long as that block confguration is selected. the region of the array outside the block protection can only be modifed if write enable (wen) is set to 1. therefore, it may be necessary that a wren instruction occur prior to write. hardware write pro tection has no affect on the memory array. once write is completed, wen is reset for complete chip write protec tion. (see figure 7 for timing). table 4. write protection wpen wp hardware write wen inside block outside block status register protection (wpen, bp1, bp0) 0 not enabled 0 read-only read-only read-only 0 not enabled 1 read-only unprotected unprotected 1 0 enabled 0 read-only read-only read-only 1 0 enabled 1 read-only unprotected read-only 1 not enabled 0 read-only read-only read-only 1 not enabled 1 read-only unprotected unprotected note: x = don't care bit.
integrated silicon solution, inc. 7 preliminary information rev. 00a 01/26/09 is25c16 absolute maximum ratin gs (1) symbol parameter value unit v s supply voltage -0.5 to + 6.5 v v p voltage on any pin C0.5 to vcc + 0.5 v t b i a s temperature under bias C55 to +125 c t s t g storage temperature C65 to +150 c i o u t output current 5 ma notes: 1. stress greater than those listed under absolute maximum ratings may cause perma - nent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. operatin g range (is25c16-2) range ambient temperature v c c industrial C40c to +85c 1.8v to 5.5v note: issi offers industrial grade for commercial applications (0 o c to +70 o c). capacitance (1,2) s ymbol parameter conditions max. unit c i n input capacitance v i n = 0v 6 pf c o u t output capacitance v o u t = 0v 8 pf notes: 1. tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. test conditions: t a = 25c , f = 1 mhz, vcc = 5.0v. operatin g range (is25c16-3) range ambient temperature v c c automotive C40c to +125c 2.5v to 5.5v
8 integrated silicon solution, inc. preliminary information rev. 00a 01/26/09 is25c16 dc electrical characteristics t a = C40c to +85c for industrial, t a = C40c to +125c for automotive. symbol parameter test conditions min. max. unit v o l 1 output low voltage v c c = 5v, i o l = 2 ma 0.4 v v o l 2 output low voltage v c c = 2.5v, i o l = 1.5 ma 0.4 v v o l 3 output low voltage v c c = 1.8v, i o l = 0.15 ma 0.2 v v o h1 output high voltage v c c = 5v, i o h = -2 ma 0.8 x v c c v v o h2 output high voltage v c c = 2.5v, i o h = -0.4ma 0.8 x v c c v v o h3 output high voltage v c c = 1.8v, i o h = -0.1ma 0.8 x v c c v v i h input high voltage 0.7 x v c c v c c + 1 v v i l input low voltage -0.3 0.3 x v c c v i l i input leakage current v i n = 0v t o v c c -2 2 a i l o output leakage current v o u t = 0v t o v c c , cs = v c c -2 2 a power supply characteristics - industrial t a = C40c to +85c symbol parameter test conditions min. max. unit i c c 1 operating current read/write at 10 mhz (vcc = 5v) 5.0 ma i c c 2 operating current read/write at 5 mhz (vcc = 2.5v) 3.0 ma i c c 3 operating current read/write at 2 mhz (vcc = 1.8v) 1.0 ma i s b 1 standby current vcc = 5.0v, v i n = v c c or gnd 3.0 a cs = vcc i s b 2 standby current vcc = 2.5v, v i n = v c c or gnd 2.0 a cs = vcc i s b 3 standby current vcc = 1.8v, v i n = v c c or gnd 1.0 a cs = vcc power supply characteristics - automotive t a = C40c to +125c symbol pa rameter test conditions min. max. unit i c c 1 operating current read/write at 5 mhz (vcc = 5v) 4.0 ma i c c 2 operating current read/write at 5 mhz (vcc = 2.5v) 3.0 ma i s b 1 standby current vcc = 5.0v, v i n = v c c or gnd 8.0 a cs = vcc i s b 2 standby current vcc =2.5v, v i n = v c c or gnd 5.0 a cs = vcc
integrated silicon solution, inc. 9 preliminary information rev. 00a 01/26/09 is25c16 ac characteristics - industrial t a = C40c to +85c supply voltage = 1.8v to 5.5v 1.8v vcc < 2.5v 2.5v vcc < 4.5v 4.5v vcc 5.5v symbol parameter min max min max min max units f sck sck clock frequency 0 2 0 5 0 10 mhz t ri input rise time 2 2 2 s t fi input fall time 2 2 2 s t wh sck high time 200 90 40 ns t wl sck low time 200 90 40 ns t cs cs high time 200 100 40 ns t css cs setup time 200 90 40 ns t csh cs hold time 200 90 25 ns t su data in setup time 40 20 15 ns t h data in hold time 50 30 15 ns t hd hold setup time 100 50 25 ns t cd hold rotime 100 50 25 ns t v output valid 0 150 0 60 0 25 ns t ho output hold time 0 0 0 ns t lz hold to output low z 0 100 0 50 0 25 ns t hz hold to output high z 250 100 25 ns t dis output disable time 250 100 25 ns t wc write cycle time 10 5 5 ms notes: c l = 100pf
10 integrated silicon solution, inc. preliminary information rev. 00a 01/26/09 is25c16 ac characteristics - automotive t a = C40c to +125c. supply voltage = 2.5v to 5.5v 2.5v vcc < 4.5v 4.5v vcc 5.5v symbol parameter min max min max units f sck sck clock frequency 0 5 0 10 mhz t ri input rise time 2 2 s t fi input fall time 2 2 s t wh sck high time 90 40 ns t wl sck low time 90 40 ns t cs cs high time 100 40 ns t css cs setup time 90 40 ns t csh cs hold time 90 25 ns t su data in setup time 20 15 ns t h data in hold time 30 15 ns t hd hold setup time 50 25 ns t cd hold rotime 50 25 ns t v output valid 0 60 0 25 ns t ho output hold time 0 0 ns t lz hold to output low z 0 50 0 25 ns t hz hold to output high z 100 25 ns t dis output disable time 100 25 ns t wc write cycle time 5 5 ms notes: c l = 100pf
integrated silicon solution, inc. 11 preliminary information rev. 00a 01/26/09 is25c16 timing dia grams figure 3. wrdi timing figure 2. wren timing figure 1. synchronous data timing cs sk d in d out v ih v il v ih v il v ih v il v oh v ol va lid in high-z high-z t css t wh t wl t h t su t cs t csh t v t ho t dis high-z wren op-code cs sk d in d out high-z wrdi op-code cs sk d in d out
12 integrated silicon solution, inc. preliminary information rev. 00a 01/26/09 is25c16 figure 6. read timing figure 5. wrsr timing figure 4. rdsr timing cs sk din dout instr uction 7 6 5 4 3 2 1 0 da ta out cs sk din dout instr uction 7 6 5 4 3 2 1 0 d ata in 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sk din dout instr uction byte address 7 6 5 4 3 2 1 0 da ta out
integrated silicon solution, inc. 13 preliminary information rev. 00a 01/26/09 is25c16 figure 8. hold timing figure 7. write timing 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cs sk din dout instr uction byte address da ta in cs sck hold d out t cd t hd t hz t lz t hd t cd
14 integrated silicon solution, inc. preliminary information rev. 00a 01/26/09 is25c16 automotive range: C40c to +125c, lead-free v oltage range part number package 2.5v is25c16-3gla3 150-mil soic (jedec) to 5.5v is25c16-3zla3 3 x 4.4 mm tssop ordering information industrial range: -40c to +85c, lead-free voltage range part number package* (8-pin) 1.8v is25c16-2gli 150-mil soic (jedec) to 5.5v is25c16-2zli 3 x 4.4 mm tssop is25c16-2dli-tr 2 x 3 mm dfn IS25C16-2CLI* csp * 1. contact issi sales representatives for availability and other package information. 2. most listed part numbers are packed in tube, except dfn in tape and reel -tr. 3. for tape and reel, add -tr at the end of the p/n (4k per reel). dfn is 5k per reel. 4. refer to issi website for related declaration document on lead free, rohs, halogen free, or green, whichever is applicable. 5. issi offers industrial grade for commercial applications (0 o c to +70 o c).
integrated silicon solution, inc. 15 preliminary information rev. 00a 01/26/09 is25c16
16 integrated silicon solution, inc. preliminary information rev. 00a 01/26/09 is25c16 integrated silicon solution, inc. packaging information thin shrink small outline tssop package code: z (8 pin, 14 pin) rev b 02/01/02 tssop (z) ref. std. jedec mo-153 no. leads 8 millimeters inches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.032 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.004 0.008 d 2.90 3.10 0.114 0.122 e1 4.30 4.50 0.169 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.018 0.030 ? 8 ? 8 tssop (z) ref. std. jedec mo-153 no. leads 14 millimeters inches symbol min max min max a ? 1.20 ? 0.047 a1 0.05 0.15 0.002 0.006 a2 0.80 1.05 0.031 0.041 b 0.19 0.30 0.007 0.012 c 0.09 0.20 0.0035 0.008 d 4.90 5.10 0.193 0.201 e1 4.30 4.50 0.170 0.177 e 6.40 bsc 0.252 bsc e 0.65 bsc 0.026 bsc l 0.45 0.75 0.0177 0.0295 ? 8 ? 8 d b e e1 a2 e c a a1 l 1 n n/2 ssi reserves the right to make changes to its products at any time without notice in order to improve design and supply the bes t possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2002, integrated silicon solution, inc.
integrated silicon solution, inc. 17 preliminary information rev. 00a 01/26/09 is25c16 packaging information integrated silicon solution, inc. ? www.issi.com ? 1-800-379-4774 rev. b 02/13/06 copyright ? 2006 integrated silicon solution, inc. all rights reserved. issi reserves the right to make changes to this speci fication and its products at any time without notice. issi assumes no liability arising out of the application or use of any information, products or services desc ribed herein. customers are advised to obtain the latest version of this device specification before relying on any published information and before placing orders fo r products. dual flat no-lead package code: d (8-pad) a2 b (8x) a 1 a3 d e a l (8x) e (6x) 1.50 ref. d2 e 2 pad 1 id pad 1 index area tie bars (3) notes: 1. refer to jedec drawing mo-229. 2. this is the metallized terminal and is measured between 0.18 mm and 0.30 mm from the terminal tip. the terminal may have a straight end instead of rounded. 3. package may have exposed tie bars, ending flush with package edge. dfn millimeters sym. min. nom. max. n0. pad 8 d 2.00 bsc e 3.00 bsc d2 1.50 ? 1.75 e2 1.60 ? 1.90 a 0.70 0.75 0.80 a1 0.0 0.02 0.05 a2 ? ? 0.75 a3 0.20 ref l 0.30 0.40 0.50 e 0.50 bsc b 0.18 0.25 0.30
18 integrated silicon solution, inc. preliminary information rev. 00a 01/26/09 is25c16 csp (i) - structure of solder bump

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